CS704 Current FinalTerm Paper 20 August 2017
Q1. Small writes in RAID3 & RAID 4/5
Q2. State transition diagram of directory based, and explain your diagram
Q3. Explain the concept of cache and locality in memory hierarchy
Q4. How much fast is CPU if AVG CPI is 1.2 with instruction as hit ... as compared to one having miss penalty of 30 cycles having 40% instructions load
Q5. Wider memory and interleave memory
Q6. You are building a system around a processor with in-order execution that runs at 1.1GHz and has a CPI of 0.7 excluding memory accesses. The only instructions that read or write data from memory are loads (20% of all instructions) stores (5% of all instructions).
Q7. The memory system for this computer is composed of a split L1 cache that imposes no penalty on hits. Both the I-cache and D-cache are direct mapped and hold 32KB each. The I-cache has 2% miss rate and 32-byte blocks, and the D-cache is write through with a 5% miss rate and 16- byte blocks. There is a write buffer on the D-cache that eliminates stalls for 95% of all writes.
Q8. The 512KB write-back, unified L2 cache has 64-byte blocks and an access time of 15ns. It is connected to the L1 cache by a 128-bit data bus that runs at 266 MHz and can transfer one
Q9. 128-bit word per bus cycle. Of all memory references sent to the L2 cache in this system, 80% are satisfied without going to main memory. Also 50% of all blocks replaced are dirty.
Q10. The 128-bit-wide main memory has an access latency of 60ns, after which any number of bus words may be transferred at the rate of one per cycles on the 128-bit-wide 133 MHz main memory bus. What is the overall CPI, including memory accesses?
a) find out access time
b) find read access time
c) find write access time
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